wafer.space Community

17:50

I'm guessing my MCML SCL efforts are not particularly relevant for those/that application?

MCML?

@Lofty @Tholin

17:50

"mos current mode logic"

MUX2

um, does this use differential signalling?

stacks up to about 4~5 on sky130; probably more on gf180mcu due to higher voltage margins allowing for more stacked nmos to be in saturation, at least if there's near-zero-native-threshold voltage devices that can be placed in a raised pwell

Lofty

um, does this use differential signalling?

yes!

17:52

means inverters are free

17:53

this is a delay cell of which you can use just 2 to get a quadrature VCO

17:53

well, you want a bias generator to adjust the load to get good swing at the tail current that gives the desired frequency

so, Tholin's 3.3V static CMOS library will fit naturally into a synthesisable flow. mine will require...some finagling but is intended to be targetable by synthesis tools. I'm...much less convinced about the feasibility of dual-rail logic from a synthesis tool. Of course people can hand-design all they want, but I think both Tholin and I want a library which is "good enough" for people.

I'm trying to get the TX part of a serdes onto my tile on ttsky26a and would be porting the design to wafer.space Run2. I'd expect to get a sprinkle of SCL done for the fall ttsky26

Lofty

so, Tholin's 3.3V static CMOS library will fit naturally into a synthesisable flow. mine will require...some finagling but is intended to be targetable by synthesis tools. I'm...much less convinced about the feasibility of dual-rail logic from a synthesis tool. Of course people can hand-design all they want, but I think both Tholin and I want a library which is "good enough" for people.

wdym dual-rail?

"dual-rail" is the term for differential logic inside an integrated circuit

the cells once done as actual SCL blocks are just sipped with what currently looks to be a second metal trace over or right adjacent to the Vdd and GND power rails of a normal SCL footprint setup.

17:58

The GND-side one is the tail bias; the Vdd-side one is the PMOS active tie one; that one is skippable in exchange for loosing the ability to dial power-delay-product without having to do dynamic Vdd scaling.

Lofty

"dual-rail" is the term for differential logic inside an integrated circuit

ohhhh

17:59

(I mean I'm pretty sure it can be routed as just a double-pitch track on the usual DRCs for metal corners.)

um, not what I meant, exactly.

But yes, sure. The bigger hurdle would likely be to teach yosys that some cells exist but are often slower than decomposing (not always, and usually not smaller).

Well, that's the job of the liberty library.

Lofty

um, not what I meant, exactly.

Are you suggesting that yosys would have more fundamental issues coping with the concept of free inversion?

Lofty

Well, that's the job of the liberty library.

can't google

namibj

Are you suggesting that yosys would have more fundamental issues coping with the concept of free inversion?

I'm... going to assume this was asked in good faith and you're not trying to imply I don't know how inverters work.

namibj

can't google

https://people.eecs.berkeley.edu/~alanmi/publications/other/liberty07_03.pdf It's a specification by Synopsis that basically all standard cell libraries use (sky130, gf180mcu, ihp sg13g2...)

Lofty

I'm... going to assume this was asked in good faith and you're not trying to imply I don't know how inverters work.

No I'm well aware you know yosys and almost certianly the gate names way better than me.

18:07

But without differential logic it's AFAIK not the case that inversion is (close enough to) free.

Lofty

I'm... going to assume this was asked in good faith and you're not trying to imply I don't know how inverters work.

So, ABC flatly does not understand differential logic, so you have to treat your differential cells as single-rail (non-differential logic) for the purposes of mapping it, and then map from single-rail to dual-rail and duplicate the single-rail nets. Realistically? That means writing a Yosys pass to do that transform.

namibj

But without differential logic it's AFAIK not the case that inversion is (close enough to) free.

In domino logic inversion is free because it's impossible to express inverting functions :p

oh right forgot that single-ended companion exists

18:18

well, more like, that it (a) does exist and that (b) domino logic refers to it.

18:19

which makes them somewhat similar in synthesis considerations, though MCML isn't as forced to use a dedicated one-shot precharge

18:23

I've been more concerned with the difficulty of power gating MCML and it's near indifference to clock gating (and related, abhorrent power consumption of DFF-RAM), regarding practical usability.